1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular to self-refresh control for reducing current consumption during self-refresh operation.
2. Description of the Related Art
Recent developments in portable digital equipment have allowed such equipment to have a variety of functions. Therefore, the portable digital equipment is equipped with a large number of semiconductor devices such as a CPU, a storage device and so on. Since the portable digital equipment is driven by a battery, it is not allowed to increase its current consumption even though the number of mounted semiconductor devices is increased. Therefore, the reduction of current consumption of the semiconductor devices mounted therein is strongly desired. For example, as the functions of a cellular phone are expanded to an extent equivalent to those of a laptop computer, the demand for reduction of current consumption of a dynamic random access memory (hereafter, referred as DRAM) is being increased.
In a cellular phone, in particular, the waiting time for which the phone is in a call waiting state is considerably long in comparison with the use time. Therefore, the reduction of current consumption during this waiting time is important. On the other hand, a DRAM requires a refresh operation for holding stored information even during the waiting time. A refresh operation performed during the waiting time is referred to as a self-refresh operation. The self-refresh operation is carried out automatically by the DRAM itself. The reduction of current consumption in the DRAM is therefore achieved by suppressing the refresh current flowing through a cell, and reducing the direct current flowing constantly. The suppressing of the refresh current is achieved by setting the interval between refreshes as long as possible, in other words, by minimizing the leak current from the cell.
The direct current mentioned in the above consists of a direct current flowing to a power supply circuit within the DRAM, a total of all the transistor leak currents within the DRAM, and a defect current within the DRAM. The reduction of the direct current has been conventionally achieved by reducing the direct current to the power supply circuit and the leak current in the transistors. Recently, however, the reduction of these currents has reached its maximum level, and no further reduction is possible. Accordingly, the defect current has become to draw more attention in this respect. It is obvious also from the fact that the ratio of the defect current (that is now in the order of 60 uA) to the entire current (of about 100 uA) has become greater.
For example, the potential of a word line in the standby (inactive) state is set to a negative level (negative potential) in order to reduce the leak current of the memory cell transistor. This method is referred to as a negative word line method. The reason why the potential of the word line in the inactive state is set to a negative potential is to prevent electric charge stored in the memory cell (storage node) from being leaked away due to variation in potential of a bit line. Consideration is given here to a case in which a high potential (array potential VARY) is stored in the capacity of a memory cell. When a bit line is at 0 V and a word line at a level of around 0 V, leakage of a very small amount of current occurs in the memory cell transistor so that the built-up array potential VARY is decreased. The decrease of the potential built up in the memory cell causes decrease in margin for read operation, which may finally induce a problem of read failure.
In order to reduce the leak current, the potential of the inactive word line is set to a negative potential, for example to −0.3 V. The memory cell transistor is an N-channel type transistor. When the potential of the inactive word line is set to −0.3 V, the gate potential becomes −0.3 V, the source potential becomes 0 V, and the drain potential becomes the array potential VARY In this case, the gate-source potential Vgs becomes −0.3 V, the channel is depleted, and the leak current is reduced. The potential of the inactive word line, or −0.3 V is represented as the negative potential VKK. This negative potential VKK is not supplied from the outside of the DRAM chip, but supplied by being internally generated by a pump circuit provided in the DRAM chip. Since the negative potential VKK is generated by the pump circuit, the current consumption is increased by that much when current is supplied to the negative potential VKK. For example, if a current of 1 mA is supplied to the negative potential VKK, a current of 3 mA is consumed by the pump circuit to generate the same.
When there exists a short-circuit defect on a word line in the inactive state at a negative potential, the defect current problematically increases. The probability is extremely high that one of several thousands of word lines present in the DRAM will have a defect of short-circuiting with a bit line, and several or several tens of chips among several hundreds of chips have such short-circuit defect. These memory cells having the short-circuit defect are replaced by a redundancy circuit. However, the short-circuit defect is left on the chip, possibly causing a defect current. The number of the short-circuit defects is obviously associated with a proficiency of the process. There will occur a greater number of defects in an initial stage of developing the process. The word lines in the waiting state in the DRAM are at the negative potential VKK, while the bit lines are at a precharge potential. The precharge potential is a potential corresponding to a half of the potential of the array potential VARY (hereafter, referred to as half VARY). In a DRAM having a short-circuit defect, therefore, a defect current flows from the potential of the bit line (half VARY) to the word line (VKK).
This current is a loss current caused by the defect. For example, when a loss current of 300 uA flows to the negative potential VKK, a loss current in the pump circuit becomes 900 uA. Thus, a loss current of 1200 uA (1.2 mA) flows in the DRAM as a whole. A standby current of a DRAM mounted on a cellular phone is a current when the cellular phone is in standby while performing the self-refresh operation. The value of the current during the self-refresh operation (referred to as IDD6 specification) is 1 mA or lower at a temperature around 40° C. In an example of a 512M DRAM, the practical current value is about 500 uA or lower. If this value is the specification value of the DRAM, the value of the loss current is relatively too large to be allowed. Accordingly, the DRAM is rejected according to the IDD6 specification. The word line and the bit line including a short circuit are replaced by a redundancy circuit, so that the operation of the DRAM is not impaired. However, there still occurs a problem that the DRAM is rejected on the basis of the electric current specification.
There are prior patent references describing the negative word line method and refresh of the DRAM. For example, Japanese Laid-Open Patent Publication H11-144458 (Patent Reference 1) describes a technique in which the potential of a word line is set to a boosting potential VPP and a negative level Vnn. According to Japanese Laid-Open Patent Publication H11-31384 (Patent Reference 2) and Japanese Laid-Open Patent Publication 2003-30984 (Patent Reference 3), the reset potential of a word line is changed first to a ground potential and then to a negative level. According to Japanese Laid-Open Patent Publication H11-283367 (Patent Reference 4), a refresh control circuit is provided to set a refresh mode. None of these prior patent references, however, discloses or suggests the problems to be solved by the present invention or a technique to solve the problems.